Modern circuit designs implemented within ICs are typically partitioned into multiple clock domains. Each clock domain can operate at a different frequency according to the particular performance requirements of that circuit design. Part of the circuit design process includes determining the particular frequency at which each partition will operate while still ensuring the integrity and synchronization of any communications that move from one clock domain to another.
Presently, circuit designers manually determine the clock frequency of each clock domain of the circuit design. This entails a trial and error process where different frequencies for each clock domain are tested. Once a clock frequency is determined for each individual clock domain, the clock domains of the circuit design can be tested in combination. When the circuit design does not meet a design requirement, the designer manually adjusts the clock frequency of one or more domains and repeats the process. This can become a long and tedious endeavor even for circuit designs with few clock domains. While searching for a workable clock frequency for each clock domain, the designer remains unaware of whether a solution is actually feasible.